Planar view TEM sample preparation from circuit layer structures
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United States of America Patent
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Apr 24, 2007
Grant Date -
Jun 29, 2006
app pub date -
Dec 23, 2004
filing date -
Dec 23, 2004
priority date (Note) -
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Abstract
A method of preparing a planar view TEM sample of a planar portion of a circuit layer structure formed on a substrate. The method includes polishing the substrate circuit layer structure until a cross-sectional polishing face has substantially reached a first side face of the planar portion of the circuit layer structure; forming a trench structure in the cross-sectional polishing face. The trench structure extends into the cross-sectional polishing face substantially in the direction parallel to the substrate such that top and bottom faces of the planar portion of the circuit layer structure are exposed, wherein the planar portion of the circuit layer structure extends substantially parallel to the substrate from the first side face. The method further includes performing a cut around the first side face to free the planar portion of the circuit layer structure.
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