Fabrication of local interconnect lines
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United States of America Patent
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Apr 24, 2007
Grant Date -
Nov 9, 2006
app pub date -
May 5, 2005
filing date -
May 5, 2005
priority date (Note) -
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Abstract
A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.
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