Method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 17, 2007
Grant Date -
Oct 21, 2004
app pub date -
Dec 6, 2001
filing date -
Dec 8, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully