Verification of memory operations by multiple processors to a shared memory
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United States of America Patent
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Apr 3, 2007
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app pub date -
Oct 9, 2002
filing date -
Oct 9, 2002
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Abstract
A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.
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