Damascene structure with integral etch stop layer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 3, 2007
Grant Date -
Nov 4, 2004
app pub date -
Jul 15, 2002
filing date -
Jul 19, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer H.sub.2 plasma without any prior anneal prior to the deposition of the upper layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully