Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device
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United States of America Patent
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Mar 27, 2007
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N/A
app pub date -
Dec 7, 2005
filing date -
Dec 7, 2005
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Expired
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Abstract
Programming redundant columns for a multi-plane EEPROM includes identifying a defective memory column during a back-end testing operation to provide redundancy information in the form of the original address for the defective column and the address for corresponding fuse links that are programmed to access a redundant column instead of the defective column. From the address for the corresponding fuse links are provided redundant column word-line select (COL RED WL Select) signals to WL input terminals of a Column Redundancy CAM. From the address for the corresponding fuse links are provided column address decoded COL Address Decoded signals to decoded column address input terminals of the Column Redundancy CAM. All of the fuse links are simultaneously programmed.
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