Transistor, method for producing an integrated circuit and a method of producing a metal silicide layer
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United States of America Patent
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Mar 27, 2007
Grant Date -
Oct 13, 2005
app pub date -
May 24, 2002
filing date -
May 26, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.
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