Interlocking via for package via integrity
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United States of America Patent
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Mar 13, 2007
Grant Date -
Jun 29, 2006
app pub date -
Dec 27, 2004
filing date -
Dec 27, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric layer extending from a surface of the dielectric layer to the first conductive layer; providing a recess in the first conductive layer and in communication with the hole to provide an interlocking volume under the dielectric layer; providing a conductive material in the hole and in the recess to form a package via having an interlocking section in the interlocking volume of the recess; and providing a conductive material on the dielectric layer to form a second conductive layer adapted to be in electrical contact with the first conductive layer through the package via.
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