Flash/dynamic random access memory field programmable gate array
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United States of America Patent
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Mar 6, 2007
Issued Date -
N/A
app pub date -
Jul 10, 2006
filing date -
Jul 17, 2003
priority date (Note) -
Expired
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Abstract
A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.
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