Architecture for controlling dissipated power in a system-on-chip and related system
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United States of America Patent
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Feb 13, 2007
Grant Date -
Jan 29, 2004
app pub date -
May 16, 2003
filing date -
May 17, 2002
priority date (Note) -
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Abstract
A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.
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