Lateral short-channel DMOS, method for manufacturing same and semiconductor device
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United States of America Patent
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Feb 6, 2007
Grant Date -
Dec 16, 2004
app pub date -
Sep 18, 2003
filing date -
Oct 25, 2002
priority date (Note) -
Expired
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Abstract
A lateral short-channel DMOS includes an epitaxial layer formed on a semiconductor substrate. A first conductivity-type well is formed in the epitaxial layer. A second conductivity-type well is formed in the first conductivity-type well and includes a channel forming region. A source region is formed in the second conductivity-type well. A first conductivity-type ON resistance lowering well is formed in the epitaxial layer so as to contact the first conductivity-type well but not the second conductivity-type well, and includes a higher concentration of a first conductivity-type dopant than the first conductivity-type well. A drain region is formed in the first conductivity-type ON resistance lowering well. A gate electrode is formed above and insulated from at least the channel forming region.
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