Bump for semiconductor package, semiconductor package applying the bump, and method for fabricating the semiconductor package
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United States of America Patent
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Jan 30, 2007
Grant Date -
Oct 13, 2005
app pub date -
Oct 29, 2004
filing date -
Apr 8, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention discloses a bump for a semiconductor package, a semiconductor package applying the bump, and a method for fabricating the semiconductor package. As a second bump unit contacting an electrode terminal of a PCB has a smaller width than a first bump unit contacting an electrode pad of a semiconductor chip through a metal adhering layer, even if a pitch between the electrode pads of the semiconductor chip does not correspond to the pitch between the electrode terminals of the PCB, contact reliability is improved by the bump. In addition, the bump does not contact lines adjacent to the electrode terminal of the PCB, thereby preventing a mis-operation of the semiconductor package. Accordingly, the pitch between the electrode pads of the semiconductor chip and the pitch between the bumps can be minimized.
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