Vertical integrated circuits
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United States of America Patent
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Dec 5, 2006
Grant Date -
May 26, 2005
app pub date -
Dec 23, 2004
filing date -
Sep 12, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.
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