Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
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United States of America Patent
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Nov 28, 2006
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N/A
app pub date -
Oct 14, 2003
filing date -
Oct 14, 2003
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Expired
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Abstract
An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.
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