CMOS process polysilicon strip loaded waveguides with a two layer core
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United States of America Patent
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Nov 14, 2006
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N/A
app pub date -
Jul 7, 2005
filing date -
Jun 24, 2002
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Abstract
A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a two layer core made of a polysilicon strip on a silicon slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.
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