Static timing analysis approach for multi-clock domain designs
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United States of America Patent
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Nov 7, 2006
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app pub date -
Aug 12, 2003
filing date -
Aug 12, 2003
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Abstract
A method for analyzing a circuit design is disclosed. The method generally includes the steps of (A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in the circuit design, (B) calculating a plurality of delays along the paths and (C) calculating a plurality of latencies with respect to the first clock for the second clocks using the delays.
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