Functional register decoding system for multiple plane operation
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United States of America Patent
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Aug 29, 2006
Issued Date -
N/A
app pub date -
Oct 14, 2003
filing date -
Oct 14, 2003
priority date (Note) -
Expired
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Abstract
A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
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