Ethernet switching architecture and dynamic memory allocation method for the same

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United States of America Patent

PATENT NO 7088730
APP PUB NO 20030147410A1
SERIAL NO

10150252

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Abstract

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This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.

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Patent Owner(s)

Patent OwnerAddress
ADMTEK INCORPORATEDSCIENCE-BASED INDUSTRIAL PARK 1F 9 INDUSTRY E 9TH RD HSINCHU R O C

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Meng-chi Hsinchu, TW 1 2
Lo, Wei-ren Hsinchu, TW 9 60

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