Light scattering structures formed in upper layer of strip loaded waveguides

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United States of America Patent

PATENT NO 7082245
SERIAL NO

11182134

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Abstract

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In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

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Patent Owner(s)

Patent OwnerAddress
CISCO TECHNOLOGY INC170 WEST TASMAN DRIVE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gunn, III Lawrence C Encinitas, CA 55 1529
Pinguet, Thierry J Cardiff-By-The-Sea, CA 47 1317
Rattier, Maxime Jean Paris, FR 30 564

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