Clock balanced segmentation digital filter provided with optimun area of data path
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United States of America Patent
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May 9, 2006
Grant Date -
Feb 12, 2004
app pub date -
Aug 9, 2002
filing date -
Aug 9, 2002
priority date (Note) -
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Abstract
The present invention generally relates to provide a clock balanced segmentation digital filter, which is provided with an optimum area of a data path. The digital filter includes a controlling unit, which is connecting with a register, a multiplexer unit, and an arithmetic and logic unit. The present invention utilizes the controlling unit to initialize the filter parameter stored in the register and to segment the whole logic operation procedure to a plurality of operation steps and to arrange the operation procedure. The multiplexer unit is connecting with the register and the arithmetic and logic unit. The multiplexer unit controlled by the controlling unit is choosing the require parameter and data to output into the arithmetic and logic unit to perform the operation. The operation result is stored in the register for using as the following operation parameter. The present is provided with advantages of scaling down the area of logic circuit, low power consumption and rapid operation.
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