Glitch-free memory address decoding circuits and methods and memory subsystems using the same
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United States of America Patent
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Apr 18, 2006
Grant Date -
N/A
app pub date -
Aug 13, 2002
filing date -
Aug 13, 2002
priority date (Note) -
Expired
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Abstract
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.
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