Method, device and system for output impedance calibration that invariably maximizes hybrid performance
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United States of America Patent
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Apr 18, 2006
Grant Date -
Mar 31, 2005
app pub date -
Aug 20, 2004
filing date -
Sep 26, 2003
priority date (Note) -
Expired
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Abstract
A hybrid system with adjustable on-chip components and a method calibrating the same invariably maximizes hybrid performance despite of on- and off-chip component mismatches and imperfections. The hybrid system has a main DAC, a replica DAC, and three or four resistors. Both DACs are directly connected to digital data. An adjustable resistor is connected to the main DAC and is calibrated such that output impedance is automatically adjusted to match an off-chip load impedance Z. A replica DAC current K is calibrated for optimum DC matching in presence of Z. An adjustable capacitor C2 is calibrated for slope-matching (bandwidth matching). If Z changes, the calibration procedure should be repeated for optimal performance. These three calibration mechanisms can be utilized individually or in combination. The present invention is compatible with both analog and digital echo-cancellers.
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