Semiconductor memory device
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United States of America Patent
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Apr 11, 2006
Grant Date -
Dec 15, 2005
app pub date -
Jun 15, 2005
filing date -
Jun 15, 2004
priority date (Note) -
Expired
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Abstract
In a semiconductor memory device having a crosspoint-type memory cell array, each reference level between two adjacent memory levels when memory levels of multi-level information stored in a memory cell are arranged in order of size of resistance values of a corresponding variable resistive element is defined by a reference current in a middle state between a first and a second current states. In the first current state, a readout current of high resistance selected cell in which the resistance is higher in the two adjacent memory levels becomes the largest state depending on a distribution pattern of a resistance state of the other unselected cell. In the second current state, a readout current of low resistance selected cell in which the resistance is lower in the two adjacent memory levels becomes a smallest state depending on a distribution pattern of a resistance state of the other unselected memory cell.
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