Array architecture and operation methods for a nonvolatile memory
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United States of America Patent
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Feb 28, 2006
Grant Date -
N/A
app pub date -
Dec 22, 2003
filing date -
Dec 23, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.
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- 11 Citation Count
- G11C Class
- 40.48 % this patent is cited more than
- 19 Age