Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
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United States of America Patent
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Feb 21, 2006
Grant Date -
May 2, 2002
app pub date -
Jun 29, 2001
filing date -
Jun 30, 2000
priority date (Note) -
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Abstract
The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
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