Apparatus having pattern scrambler for testing a semiconductor device and method for operating same
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United States of America Patent
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Feb 21, 2006
Grant Date -
Jan 2, 2003
app pub date -
Jan 4, 2002
filing date -
Jul 2, 2001
priority date (Note) -
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Abstract
A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.
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