MOSFET device with nanoscale channel and method of manufacturing the same

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United States of America Patent

PATENT NO 6995452
SERIAL NO

10749749

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Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused. Therefore, no crystal defect of a substrate is caused, thereby decreasing a junction leakage current.

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Patent OwnerAddress
UNILOC 2017 LLC1209 ORANGE STREET WILMINGTON DE 19801

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cho, Wonju Daejeon, KR 5 118
Im, Kiju Daejeon, KR 10 96
Lee, Seong Jae Daejeon, KR 52 367
Oh, Jihun Daejeon, KR 12 33
Yang, Jong Heon Daejeon, KR 24 174

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