Process of forming high-k gate dielectric layer for metal oxide semiconductor transistor
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United States of America Patent
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Jan 31, 2006
Grant Date -
Jul 21, 2005
app pub date -
May 5, 2004
filing date -
Jan 20, 2004
priority date (Note) -
Expired
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Abstract
A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.
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