Method of electrical characterization of a silicon-on-insulator (SOI) wafer
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United States of America Patent
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Jan 31, 2006
Grant Date -
May 5, 2005
app pub date -
Nov 5, 2003
filing date -
Nov 5, 2003
priority date (Note) -
Expired
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Abstract
A method of characterizing a silicon-on-insulator (SOI) wafer, comprised of an insulating layer sandwiched between a semiconductor top layer and a semiconductor substrate, includes moving a pair of spaced conductors into contact with a surface of the wafer exposed on a side thereof opposite the substrate. First and second biases are applied to the substrate and at least one of the conductors. At least one of the first and second biases are swept from a first value toward a second value and the current flowing through the SOI wafer in response to said sweep is measured. At least one characteristic of the wafer is determined from the measured current as a function of the one swept bias.
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