Image-signal processing apparatus for clamping analog image signal and then for converting it to digital image signal
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United States of America Patent
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Jan 24, 2006
Grant Date -
Jan 2, 2003
app pub date -
Apr 25, 2002
filing date -
May 11, 2001
priority date (Note) -
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Abstract
An analog Y signal input from an input terminal 101 is clamped at a pedestal level in a clamp circuit 102, and then, is converted to a digital image signal in a quantization circuit 103. The pedestal level Dp of the digital output D(t) 113 is stored in a register 702. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter 802. The subtraction output 806 is subtracted from the digital output 113 in a subtracter 803. The subtraction output 805 (D(t)-(Dp-Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit 102 and the quantization circuit 103 has been compensated for. The subtraction output 805 is limited to a predetermined dynamic range by an overflow limiter circuit 807, and output as Dout.
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