Integrated circuit selective power down protocol based on acknowledgement

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6986074
APP PUB NO 20020152407A1
SERIAL NO

10010738

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Abstract

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A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.

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Patent Owner(s)

Patent OwnerAddress
ERIDANUS TECHNOLOGIES INC15090 AVENUE OF SCIENCE SUITE 103 SAN DIEGO CA 92128

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alia, Michele Giarre, IT 2 75
Carrano, Michele Valverde, IT 2 94
Pistritto, Carmelo Catania, IT 7 92

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