Cell modeling in the design of an integrated circuit
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United States of America Patent
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Jan 10, 2006
Grant Date -
Dec 26, 2002
app pub date -
Jun 11, 2001
filing date -
Jun 11, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.
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