Chip-scaled package having a sealed connection wire
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United States of America Patent
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-
Dec 6, 2005
Grant Date -
Dec 12, 2002
app pub date -
May 31, 2002
filing date -
Jun 12, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A chip-scaled package and manufacturing method thereof including a semiconductor chip having a chip pad thereon, a first insulating layer formed on the semiconductor chip and having an opening part exposing the chip pad, a metal wire of which one end covers the opening part so as to be electrically connected to the chip pad 202, a second insulating layer on the first insulating layer including the opening part, the second insulating layer exposing the other end of the metal wire, a conductive ball formed on the other end of the exposed metal wire, and a substrate on which the ball is to be mounted, thereby enabling to improve a package reliance by decreasing the scale and weight of the package.
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