Clock recovery PLL
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United States of America Patent
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Oct 25, 2005
Grant Date -
Apr 18, 2002
app pub date -
Dec 14, 2000
filing date -
Dec 17, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.
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