Power-rail ESD clamp circuit for mixed-voltage I/O buffer
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United States of America Patent
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Oct 11, 2005
Grant Date -
Sep 15, 2005
app pub date -
Apr 30, 2004
filing date -
Mar 12, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.
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