Phase comparator circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 13, 2005
Grant Date -
Apr 4, 2002
app pub date -
Sep 21, 2001
filing date -
Sep 29, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data signal DATA is captured by flip-flops 10 and 11 alternately every half cycle time of a clock signal CLK, outputs of the flip-flops 10 and 11 are delayed by respective delay circuits 15 and 16 to generate delayed signals 10QD and 11QD, and an output of the flip-flop 10 and the delayed signal 11QD are provided to an XOR gate 18, while an output of the flip-flop 11 and the delayed signal 10QD are provided to an XOR gate 17. The delay times of the delay circuits may be variable. Furthermore, outputs of the XOR gates 17 and 18 may be captured by the respective flip-flops alternately every half-cycle time of a delayed clock signal obtained by delaying the clock signal CLK.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully