Semiconductor device manufacturing method and semiconductor manufacturing apparatus
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United States of America Patent
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Sep 13, 2005
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app pub date -
Oct 24, 2001
filing date -
Sep 4, 1998
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Abstract
A hemispherical grain (HSG) formation process for enlarging the surface area of a capacitor electrode, wherein stable, defect-free HSG, having outstanding selectivity, is formed. An amorphous silicon layer, which constitutes a capacitor electrode, is formed on an Si wafer, on which is formed a silicon-based dielectric layer, which constitutes an interlevel dielectric layer. An HSG layer, in which there exists practically no defects, is formed on the amorphous silicon layer at a crystal nuclei formation temperature of under 620° C. Further, in accordance with properly controlling the crystal nuclei formation temperature, and the flow rate of monosilane (SiH4), which is supplied for crystal nuclei formation, it is possible to furnish selectivity such that HSG nuclei are formed solely on the amorphous silicon layer, without being formed on a silicon-based dielectric layer.
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