Three-dimensional integrated semiconductor devices
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United States of America Patent
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Sep 13, 2005
Grant Date -
Jul 10, 2003
app pub date -
Sep 30, 2002
filing date -
Jan 8, 2002
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Abstract
The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.
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