Semiconductor memory device with reduced data access time
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United States of America Patent
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Aug 30, 2005
Grant Date -
May 6, 2004
app pub date -
Oct 28, 2003
filing date -
Oct 29, 2002
priority date (Note) -
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Abstract
A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
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