Memory circuit with dynamic redundancy
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 23, 2005
Grant Date -
Jan 29, 2004
app pub date -
Jan 16, 2003
filing date -
May 30, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully