Semiconductor device with double sidewall spacer and layered contact

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United States of America Patent

PATENT NO 6914309
APP PUB NO 20030052375A1
SERIAL NO

10251062

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Abstract

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A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

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Patent Owner(s)

Patent OwnerAddress
LONGITUDE LICENSING LIMITEDBRACKEN ROAD SANDYFORD FIRST FLOOR BLACKTHORN EXCHANGE DUBLIN D18 P3Y9

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Koga, Hiroki Tokyo, JP 47 257

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