Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance

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United States of America Patent

PATENT NO 6911707
SERIAL NO

09207972

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Abstract

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An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES INC901 THOMPSON PLACE P O BOX 3453 SUNNYVALE CA 94088

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fulford, Jr H Jim Austin, TX 187 5367
Gardner, Mark I Cedar Creek, TX 677 11091
Kwong, Dim-Lee Austin, TX 28 1062

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