Buffer management architecture and method for an infiniband subnetwork
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 7, 2005
Issued Date -
N/A
app pub date -
Sep 30, 2002
filing date -
Sep 30, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses. The tags allow the memory allocation and deallocation process to correctly handle good and bad packets, as well as successive blocks within a data packet.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully