Electric circuit arrangement and method for checking the intactness of a photodiode array
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United States of America Patent
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May 3, 2005
Grant Date -
Jan 8, 2004
app pub date -
Apr 22, 2003
filing date -
May 7, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electric circuit arrangement and method for checking intactness of both a photodiode array and an electrical connection between an array output and a microprocessor input. The array output has a high resistance when the array is inactive and intact. In case of array error, the array output is connected via in each case a defined internal resistance to ground and supply voltages. The circuit arrangement enables at any time an assessment of the status of the connection and, if the connection is intact, enables an assessment of array intactness. This is achieved by connecting the array output via a first test resistor arranged in the spatial vicinity of the array to the ground voltage and by connecting the microprocessor input via a second test resistor arranged in the spatial vicinity of the microprocessor to a microprocessor port output which can be connected either to the ground or supply voltages.
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