Double-gate FinFET device and fabricating method thereof
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United States of America Patent
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Apr 26, 2005
Grant Date -
Aug 5, 2004
app pub date -
Feb 4, 2003
filing date -
Feb 4, 2003
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Abstract
The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction. The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.
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