PC and ATE integrated chip test equipment
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United States of America Patent
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Apr 19, 2005
Grant Date -
Dec 4, 2003
app pub date -
Aug 8, 2002
filing date -
May 30, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.
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