Method for laser cleaning of a substrate surface using a solid sacrificial film
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United States of America Patent
Stats
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Apr 19, 2005
Grant Date -
N/A
app pub date -
Oct 29, 1999
filing date -
Oct 29, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved semiconductor wafer processing apparatus 10 includes a series of processing stations combined in one form, coupled together by computer-controlled cluster tooling. Wafers are supplied in a pod to an input station 28 which initiates a data record for recording processing results at each station. A sacrificial film 140 is applied to the surface 135 of each wafer. Individual wafers are transferred to a computer-controlled defect-mapping station 14 where particulate defects 130 are identified and their position coordinates recorded. Defect-mapped wafers are transferred to a computer-controlled laser area cleaning station 11 which lifts the defects and sweeps the wafer surface clean, except for stubborn defects. Clean wafers are transferred to a final mapping station 20 or 22, followed by transfer of the wafers to an output station 30. Wafers having remaining stubborn defects are transferred to a second defect-mapping station 16 where stubborn defects are located by coordinates, after which the wafers are transferred to a defect review tool incorporating a scanning electron microscope (SEM-DRT) 24. A SEM image review of stubborn defects includes chemical analysis of the stubborn defects. A laser point-cleaning station 13 lifts and sweeps each stubborn defect individually from the wafer surface. Cleaned wafers are transferred to a third defect-mapping station 18 for recording any stubborn defects remaining, then to a second laser area cleaning station 12 for a final cleaning, followed by transfer of the wafers to a final mapping station 20 or 22 for mapping of any remaining stubborn defects. The accompanying data records are updated followed by transfer of the wafers to an output station 30.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SII SEMICONDUCTOR CORPORATION | 8 NAKASE 1-CHOME MIHAMA-KU CHIBA-SHI CHIBA 261-8507 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Castrucci, Paul P | 41 Pheasant Way, South Burlington, VT 05403 | 2 | 96 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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