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Country	kind	publication No.	Filing Date	Type	Sub-Type
AT	B	AT410188	Jan 18, 2001	Patent	Grant
Type : Patent Sub-Type : Grant
PATENT SPECIFICATION		SCHNEIDWERKZEUG UND WENDESCHNEIDPLATTE		Feb 25, 2003
EP	B1	EP1224992	Jan 17, 2002	Patent	Grant
Type : Patent Sub-Type : Grant
Patent		Schneidwerkzeug und Wendeschneidplatte		Jul 05, 2006

• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
BOHLERIT GES M B H & CO KG	WERK VI A-8605 KAPFENBERG

International Classification(s)

• B23B:TURNING; BORING
• B23C:MILLING

• 2002 Application Filing Year
• B23B Class
• 445 Applications Filed
• 195 Patents Issued To-Date
• 43.83 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Melcher, Gerhard	Frohnleiten, AT	17	140
# of filed Patents : 17 Total Citations : 140
Schlemmer, Armin	Kapfenberg, AT	3	29
# of filed Patents : 3 Total Citations : 29

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Patent Citation Ranking

• 4 Citation Count
• B23B Class

• 2.87 % this patent is cited more than
• 20 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
April 12, 2005	US,6877935,B2   US6877935B2	GRANTED PATENT AS SECOND PUBLICATION
July 18, 2002	US,20020094245,A1   US20020094245A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 4892836

Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices

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Abstract

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This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

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Description

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Claims

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Claims data not available

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Legal Events

 

• FPAY2001
• FPAY1997
• FPAY1993
• I1990
• STCF1989
• F1987
• AS1987
• PD1986

Date	Code	Event	Description
Jun 21, 2001	FPAY	FEE PAYMENT	year of fee payment: 12
Jun 26, 1997	FPAY	FEE PAYMENT	year of fee payment: 8
Jun 24, 1993	FPAY	FEE PAYMENT	year of fee payment: 4
Jan 09, 1990	I	Issuance
Nov 06, 1989	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Mar 23, 1987	F	Filing
Mar 10, 1987	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ANDREINI, ANTONIO;CONTIERO, CLAUDIO;GALBIATI, PAOLA;REEL/FRAME:004695/0110 Owner name: SGS MICROELETTRONICA S.P.A., STRADALE PRIMSOLE 50 Effective Date: Mar 10, 1987
Mar 27, 1986	PD	Priority Date