Reset control system and method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6877112
SERIAL NO

09678733

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Abstract

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An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset the emulator (30).

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITED1-1 KAMIKODANAKA 4-CHOME NAKAHARA-KU KAWASAKI-SHI KANAGAWA 211-8588

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hirose, Yoshio Kawasaki, JP 33 311
Iino, Hideyuki Kawasaki, JP 16 228
Ryu, Ken Shinagawa, JP 4 92
Utsumi, Hiroyuki Kawasaki, JP 18 102

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