Method of fabricating flash EEPROM
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 22, 2005
Grant Date -
Jul 3, 2003
app pub date -
Dec 26, 2002
filing date -
Dec 29, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A flash EEPROM cell and fabricating method thereof. The cell comprises: a silicon substrate; a silicon pillar layer formed on the silicon substrate; a tunnel insulating film and a floating electrode, formed on the silicon pillar layer; a control gate insulating film and a control gate electrode, formed on the floating electrode; a source region formed in the silicon substrate; a drain region formed on the silicon pillar layer; and bit lines formed on the drain region. The method comprises: providing a silicon substrate; forming a silicon pillar layer on the silicon substrate; forming a tunneling insulating film and a floating electrode; successively forming a control gate insulating film and a control gate electrode; forming a source region and a drain region in the silicon substrate, and on the silicon pillar layer, respectively; and forming bit lines.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully